1. Field of the Invention
The present invention relates to a load driving circuit, a driver IC having a load driving circuit, and a plasma display panel having a driver IC.
2. Description of the Related Art
Nowadays, plasma display panels (hereinafter abbreviated as PDPs), which enable size increases and thickness and weight reduction, are attracting much attention as display devices used in TV receivers and personal computers. And the tendencies toward screen size to 50 inches or more and increases in resolution as exemplified by the spread of full Hi-Vision TV receivers, are accelerating. Accordingly, panel driving circuits are now required to carry increased drive currents and to perform high-speed switching operations. For example, a voltage of 140 V is switched at as high a speed as 60 ns. An instantaneous current flowing in such a case is estimated as follows by assuming a triangular wave. Assume that the capacitance per scanning line of a panel is 250 pF. Since the number of full Hi-Vision scanning lines is 1,080, an instantaneous current is calculated as 2×(140 V×250 pF×1,080 lines)/60 ns=1,260 A. In an actual circuit, such a large instantaneous current is not measured because many resistance components and inductance components are involved and hence temporal deviations occur between circuit blocks. However, the probability that a large instantaneous current will cause noise or an erroneous operation is high
FIG. 20 shows a general configuration of an exemplary PDP driving device. For the sake of simplicity, this PDP driving device is for a 2-electrode PDP.
The driving device for a PDP 700 is composed of plural scan driver ICs (integrated circuits) 800-1, 800-2, 800-3, . . . , 800-k, data (address) driver ICs 900-1, 900-2, 900-3, . . . , 900-l, etc. (k and l are arbitrary numbers).
Each of the scan driver ICs 800-1 to 800-k drives plural scan/maintaining electrodes 911 and each of the data (address) driver ICs 900-1 to 900-l drives plural data electrodes 912 which correspond to the respective colors R, G, and B. The scan/maintaining electrodes 911 and the data electrodes 912 are arranged perpendicularly to each other in lattice form and discharge cells (not shown) are disposed at their crossing points.
For example, in the case of XGA (extended video graphics array) in which the PDP 700 has 1,024×768 pixels, 12 scan driver ICs 800-1 to 800-k are provided (k=12) if each scan driver can drive 64 scan/maintaining electrodes 911.
In displaying an image, data on the data electrodes 912 are written to the discharge cells by the scan driver ICs 800-1 to 800-k and the data (address) driver ICs 900-1 to 900-l while a scan is performed from one scan/maintaining electrode 911 to another (an address discharge period) and the discharges are maintained by supplying discharge maintaining pulses several times to the scan/maintaining electrode 911 (a discharge maintaining period).
FIG. 11 is a circuit diagram showing a load driving circuit that is part of each scan driver IC 800 for the PDP 700 shown in FIG. 20. This circuit has an output circuit section 101 having a totem pole structure between a pair of drive voltage supply lines, a level shifter circuit 102, a control circuit 103, and a protection circuit section 104. The output circuit section 101 is configured in such a manner that a totem pole circuit having two n-channel IGBTs (insulated gate bipolar transistors, hereinafter referred to as transistors) N1 and N2 which serve as low-side and high-side main switch elements and allow passage of a large current per unit area is connected between a drive voltage supply terminal 105 to which a first drive voltage VDH is supplied and a ground terminal 106 to which a second drive voltage (GND) is supplied, and that a DC output Do is supplied to the load from an output terminal 107. A low-side diode D1 is connected, in opposite polarity, between the drain and the source of the low-side transistor N1. A high-side diode D2 is connected, in opposite polarity, between the drain of the high-side transistor N2 and the output terminal 107, and the source of the high-side transistor N2 is connected to the output terminal 107 via a forward diode D3.
The level shifter section 102 is composed of n-channel MOS (metal-oxide-semiconductor) field-effect transistors (hereinafter abbreviated as MOSFETs) N3 and N4 and p-channel MOSFETs P1 and P2. The sources of the MOSFETs P1 and P2 are connected to the high-side drive voltage supply terminal 105. The gate of the MOSFET P1 is connected to the drain of the MOSFET P2, and the drain of the MOSFET P1 is connected to the gate of the MOSFET P2. The drain of the MOSFET P1 is connected to the drain of the MOSFET N3, and the drain of the MOSFET P2 is connected to the drain of the MOSFET N4. The sources of the MOSFETs N3 and N4 are connected to the ground terminal 106. The level shifter section 102 outputs a control signal for controlling the gate voltage of the transistor N2 of the output circuit section 101 as a high-side signal from an output point which is the connecting point of the drains of the MOSFETs P1 and N3.
The control circuit 103 is connected to the gate electrode of the transistor N1 of the output circuit section 101 and supplies it with a control signal as a low-side signal. The control circuit 103 is also connected to the gates of the MOSFETs N3 and N4 of the level shifter section 102 and supplies them with low-voltage control signals for controlling the gate voltages of the MOSFETs N3 and N4, whereby the level shifter circuit 102 supplies the high-side signal to the gate electrode of the transistor N2 of the output circuit section 101. To supply a first drive voltage and a second drive voltage alternately to the load which is connected to the output terminal 107, the low-side signal and the high-side signal are supplied to the output circuit section 101 as such control voltages as turn on and off the transistors N1 and N2 complementarily. To provide high impedance for the output terminal 107, the low-side signal and the high-side signal may be supplied as such control voltages as turn off both of the transistors N1 and N2.
In supplying a first drive voltage and a second drive voltage to the load alternately, if the transistors N1 and N2 which constitute a series circuit are turned on simultaneously, the pair of drive voltage supply lines are short-circuited by the transistors N1 and N2 (arm short-circuit state). An arm short-circuit not only increases the power consumption of the output circuit section 101, but also may destroy the devices constituting the output circuit section 101 and the load itself connected to it.
In view of the above, the control circuit 103 gives an on/off time difference (dead time) to the low-side signal and the high-side signal (two control signals) so that the level of one control signal changes from the low level to the high level after a lapse of a prescribed time from a change of the level of the other control signal from the high level to the low level and vice versa. The dead time is set taking into consideration the switching characteristics of the transistors N1 and N2 and the load drive characteristic.
Incidentally, in the conventional load driving circuit, when the high-side transistor N2 is on and the output terminal 107 is outputting a high-level D0 output D0, there may occur an event that the potential of the output terminal 107 falls steeply to the ground potential (GND) due to an external surge voltage or noise produced by switching of a capacitive or inductive load as shown in FIG. 12.
In such a case, if the protection circuit section 104 is not provided, the gate-source voltage Vgs of the high-side transistor N2 becomes higher than an ordinary operation voltage to increase the current flowing through the transistor N2. If this state continues and the transistor N2 is latched up, the transistor N2 may be destroyed due to overcurrent heating.
Where the protection circuit section 104 is not provided, formerly, to make the high-side transistor N2 less prone to be destroyed, the area of the transistor N2 is made large and the breaking resistance of the transistor N2 itself is thereby increased. However, in the case of a driver IC having the load driving circuit, increase in the scale of the load driving circuit is not preferable in terms of cost reduction. Therefore, the protection circuit section 104 as described below is provided to protect the transistor N2 of the output circuit section 101 from overcurrent breaking.
The protection circuit section 104 is composed of a Zener diode D4 for protecting the gate electrode of the transistor N2, a resistor R0 for reducing the gate voltage, a p-channel MOSFET P3, and its gate resistor R1. The parallel circuit of the Zener diode D4, the resistor R0, and the MOSFET P3 is connected between the gate and the source of the transistor N2. When the potential Do of the output terminal 107 varies, the MOSFET P3 is turned on instantaneously because of its own gate-drain parasitic capacitance and the control voltage for the transistor N2 is thereby lowered, whereby occurrence of an overcurrent is prevented.
For example, JP-A-03-247114 discloses, as a technique similar to the above protection circuit section 104, an overcurrent protection circuit for an inverter semiconductor device that is a switching power device. In this protection circuit, when the Zener voltage of a Zener diode which is connected to the gate is exceeded, an auxiliary transistor of the protection circuit is turned on, whereby the gate-source voltage of the power device is lowered to a prescribed level.
JP-A-04-322123 discloses circuits in which when a gate-source control voltage of a power device such as an IGBT exceeds a Zener voltage, a MOSFET or a transistor connected between the gate and the source is turned on, whereby the gate-source voltage is held at the Zener voltage. In a load driving circuit shown in FIG. 1 of JP-A-04-322123, when the load current increases and a voltage exceeding a Zener voltage is applied between the gate and the source, a current flows through the Zener diode and a capacitor connected between the gate and the source is charged. A MOSFET is turned on and a gate current starts to flow upon the start of the charging. The control voltage is thus limited to approximately the Zener voltage.
JP-A-2003-273714 discloses a load driving circuit having the above-described protection circuit section 104 shown in FIG. 11. There is a statement to the effect that an arm short-circuit of the totem pole circuit can be prevented reliably without increasing the number of components or the circuit size.
As described above, in the protection circuit section 104 having the configuration shown in FIG. 11, when the potential of the output terminal 107 falls steeply due to an external surge or noise, the overvoltage prevention switch (MOSFET P3) which is parallel with the resistor R0 and the Zener diode D4 is turned on instantaneously. However, since in general its gate-drain parasitic capacitance is very small, if the gate voltage of the high-side transistor N2 jumps to a large extent, the instantaneous turning-on of the MOSFET P3 is insufficient to lower the gate voltage of the transistor N2 to a steady-state voltage level. Conversely, when the potential of the output terminal 107 rises rapidly, a similar phenomenon occurs in the low-side main switching element N1. That is, there is a problem that the MOSFET P3 of the protection circuit section 104 cannot be kept on for a sufficiently long time to protect the high-side transistor N2 or the low-side transistor N1.